Technical Field
The present invention generally relates to semiconductor devices and, more particularly, to vertical fin field effect transistors.
Description of the Related Art
Vertical transistors employ channel regions that are oriented generally perpendicular to the plane of an underlying substrate—as opposed to conventional transistors which generally have channel regions that are a part of, or are otherwise parallel to, the underlying substrate. This orientation has significant potential for device scaling, more transistors can fit within a given chip surface area.
However, one challenge in forming a vertical transistor is in controlling the device's gate length. The gate length determines various properties of the final device, and conventional fabrication processes result in significant variation in gate length from one device to the next.
Another challenge is that a top spacer is generally used to separate the top source/drain region of the transistor from the gate. However, this creates a parasitic capacitance between the top source/drain region and the gate, which can impede device performance.